Getting Started

1. Set Up

Introduction

Installation

Silicon Bring-Up

2. Core Concepts

Cryptographic Parameters

NTT Hardware Core

Attestation & Signatures

3. Integration

Bus Interfaces (AXI4/APB)

Hardware Drivers & HAL

Analog-In-Memory (ReRAM)

4. Advanced Guides

Side-Channel DOM Masking

Multi-Core Throughput

Foundry Tape-Out Closure

Docs Menu

1. Set Up

Introduction

Installation

Silicon Bring-Up

2. Core Concepts

Cryptographic Parameters

NTT Hardware Core

Attestation & Signatures

3. Integration

Bus Interfaces (AXI4/APB)

Hardware Drivers & HAL

Analog-In-Memory (ReRAM)

4. Advanced Guides

Side-Channel DOM Masking

Multi-Core Throughput

Foundry Tape-Out Closure

Tashkian Hardware Architecture & Specifications

Explore hardware specifications, synthesizable RTL integration manuals, PQC TPM bus interfaces, and ReRAM in-memory computing guides.

001

Set Up

Integrate NIST FIPS 203 ML-KEM and FIPS 204 ML-DSA acceleration cores into your SoC bus architecture in minutes.

002

Core Concepts

Understand polynomial multiplication, NTT scheduling, and hardware DOM masking to ensure side-channel resilience.

003

Integration

Connect standard AXI/APB bus interfaces to the PQC TPM Root-of-Trust and NVM-IMC analog compute matrices.

004

Advanced Guide

Integrate NIST FIPS 203 ML-KEM and FIPS 204 ML-DSA acceleration cores into your SoC bus architecture in minutes.

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