1. Job Description
You will drive synthesis, place-and-route (P&R), clock tree synthesis (CTS), and static timing analysis (STA) closure for Tashkian Semiconductor’s tape-out ready silicon IP across leading foundry nodes (TSMC, GlobalFoundries, Intel Foundry).
This is about delivering synthesizable collateral and sign-off quality GDSII layouts that achieve >800 MHz performance under strict power budgets.
You will work side by side with RTL designers to optimize floorplanning, manage multi-voltage domains (UPF), and enforce Domain-Oriented Masking layout rules.
2. Key Responsibilities
Execute full physical design flow from synthesized gate-level netlist to tape-out clean GDSII collateral.
Achieve timing closure at >800 MHz across multiple PVT corners, addressing signal integrity (SI) and EM/IR drop analysis.
Collaborate with RTL architects on floorplanning, power grid distribution, and Domain-Oriented Masking physical layout constraints.
Improve reliability, consistency, and performance of AI outputs
Build systems that scale from simple use cases to complex workflows
Collaborate with designers to make complex systems feel simple
Ship fast, iterate often, and refine based on real usage
3. Qualifications
Must-have:
Strong engineering fundamentals (frontend, backend, or fullstack)
Experience building and shipping real products or features
Comfortable working with APIs, data processing, and system design
Familiarity with AI tools, LLMs, or AI-powered workflows
Ability to think in systems — not just isolated features
Strong product sense — you care about usability and outcomes
Nice-to-have:
Experience building AI-powered products or integrating AI into existing systems
Familiarity with prompt design, evaluation, or output structuring
Experience with workflow automation or orchestration systems
4. Benefits
Competitive equity — join as an early technical founder and own part of what you build.
Work from anywhere with flexible hours.
Unlimited PTO and mental health days.
Annual learning & development budget.
Top-tier equipment and software tools.
Direct collaboration with founders and product leadership.
Opportunity to shape product, tech stack, and company culture from day one.
Location
Remote
Type
Contract
Department
Business
Salary
Up to $150K/year
Expired on
1. Job Description
You will drive synthesis, place-and-route (P&R), clock tree synthesis (CTS), and static timing analysis (STA) closure for Tashkian Semiconductor’s tape-out ready silicon IP across leading foundry nodes (TSMC, GlobalFoundries, Intel Foundry).
This is about delivering synthesizable collateral and sign-off quality GDSII layouts that achieve >800 MHz performance under strict power budgets.
You will work side by side with RTL designers to optimize floorplanning, manage multi-voltage domains (UPF), and enforce Domain-Oriented Masking layout rules.
2. Key Responsibilities
Execute full physical design flow from synthesized gate-level netlist to tape-out clean GDSII collateral.
Achieve timing closure at >800 MHz across multiple PVT corners, addressing signal integrity (SI) and EM/IR drop analysis.
Collaborate with RTL architects on floorplanning, power grid distribution, and Domain-Oriented Masking physical layout constraints.
Improve reliability, consistency, and performance of AI outputs
Build systems that scale from simple use cases to complex workflows
Collaborate with designers to make complex systems feel simple
Ship fast, iterate often, and refine based on real usage
3. Qualifications
Must-have:
Strong engineering fundamentals (frontend, backend, or fullstack)
Experience building and shipping real products or features
Comfortable working with APIs, data processing, and system design
Familiarity with AI tools, LLMs, or AI-powered workflows
Ability to think in systems — not just isolated features
Strong product sense — you care about usability and outcomes
Nice-to-have:
Experience building AI-powered products or integrating AI into existing systems
Familiarity with prompt design, evaluation, or output structuring
Experience with workflow automation or orchestration systems
4. Benefits
Competitive equity — join as an early technical founder and own part of what you build.
Work from anywhere with flexible hours.
Unlimited PTO and mental health days.
Annual learning & development budget.
Top-tier equipment and software tools.
Direct collaboration with founders and product leadership.
Opportunity to shape product, tech stack, and company culture from day one.
Location
Remote
Type
Contract
Department
Business
Salary
Up to $150K/year
Expired on
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[#post-quantum]
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[#silicon-trust]
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[#post-quantum]
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[#silicon-trust]
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[#post-quantum]
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[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
Evaluate Silicon IP in Minutes
Silicon IP,
Request RTL Evaluation Today!
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//
[#post-quantum]
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[#silicon-trust]
//
[#post-quantum]
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[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
Evaluate Silicon IP in Minutes
Silicon IP,
Request RTL Evaluation Today!
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
Evaluate Silicon IP in Minutes
Silicon IP,
Request RTL Evaluation Today!
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]
//
[#post-quantum]
&
[#silicon-trust]